“RISC and CISC are merely different design methodologies. Neither is inherently superior to the other.” (Lloyd Borrett [1]) CISC architecture aims to provide simple methods for complex CPU side operations which called complex instructions. On the other hand, RISC architecture engineered to receive more simple instructions. So, on the software side, the Assembly code will be more complex for RISC based design to achieve the same operation in comparison to CISC one.
For example, if we were trying to create a simple calculator machine, probably the best choice would be to use CISC design. Thus, our CPU would have the all functions our calculator needed. We would not have to deal with extra memory components to store the Assembly codes.
The purpose of simple instructions idea is to complete each instruction in a single clock cycle. So, sets of simple instructions could be pipelined easily. Each complex instruction consists of simple instructions and then each complex instruction works in a multi clock cycle. Because, the problem of measuring a complex instruction set, pipelining is not a case for CISC.
Before delving into comparison, there is an interesting usage for the architectures I mentioned above. IBM’s RISC based RS/6000 CPU was more complex [1] than Intel’s CISC based 80386 CPU. IBM called his work as Enhanced RISC [2].
CISC versus RISC
· CISC powered system needs less RAM in comparison to RISC based system. In 70’s the RAM prices were too high. “In 1977, 1MB of DRAM cost about $5,000. By 1994, the same amount of memory cost only $6” (Crystal Chen, Greg Novick and Kirk Shimano[3])
That should be a reason to choose CISC designs in those years.
· RISC based designs work faster. Just because on the RISC side, there is a chance to know / define which registers should be remain undeleted after a single instruction. On the other hand, there is no way to interrupt or re-set complex instructions defined in CISC architecture.
· RISC based system needs more complex software codes to accomplish a goal, CISC not. (Windows 3.1)
Explicitly Parallel Instruction Computing [5]
In early 90’s, researchers realized that RISC architecture was reaching to a limit and they started to think about a new architecture. So, taking advantage of multithreading would be better than trying to accomplish more instructions per single clock cycle.
Executing every instructions in a basic order were using processor resources inefficiently. There must be a way to schedule those instructions. The architectures we mentioned above were software or hardware weighted solutions. They would be working together to create more efficient solutions. So, the goal became to move the complexity of instruction scheduling from the processor to the software side. Also, the compiler could define the operations which can be executed simultaneously. [6]
The researches were the basis for Intel Itanium architecture. The Itanium architecture is based on ILP (Instruction Level Parallelism) [7] that the execution decisions made by the compiler.
Today, we use multi-tasking supported operating systems, virtual machines and more. In fact, there are more cores inside the CPU models rather than simple multi-threading capable single core designs.
References:
[1] http://www.borrett.id.au/computing/art-1991-06-02.htm
[2] http://archive.rootvg.net/column_risc.htm
[3] http://www-cs-faculty.stanford.edu/~eroberts/courses/soco/projects/2000-01/risc/risccisc/
[4] http://en.wikipedia.org/wiki/Very_long_instruction_word
[5] http://www.hpl.hp.com/techreports/1999/HPL-1999-111.pdf
[6] http://en.wikipedia.org/wiki/Very_long_instruction_word
[7] http://en.wikipedia.org/wiki/Instruction-level_parallelism
As an answer for DQ at University of Liverpool - October 2010
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